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(parent: 10a814f) | patch
Set Verilog source location for explicit blocks (`begin` ... `end`).
authorAlberto Gonzalez <boqwxp@airmail.cc>
Fri, 17 Apr 2020 06:23:03 +0000 (06:23 +0000)
committerAlberto Gonzalez <boqwxp@airmail.cc>
Fri, 17 Apr 2020 06:23:03 +0000 (06:23 +0000)
commit00d74f0b9ceecc7b60f50fddb3b6ab0c47701923
tree1689f29481eb5ac889427035b71b2bdc05aa4782tree
parent10a814f97808de8cce7e50a03f01832db66c263ecommit | diff
Set Verilog source location for explicit blocks (`begin` ... `end`).
frontends/verilog/verilog_parser.y diff | blob | history