cpu: Added interface for vector reg file
authorRekai Gonzalez-Alberquilla <Rekai.GonzalezAlberquilla@arm.com>
Wed, 5 Apr 2017 18:24:00 +0000 (13:24 -0500)
committerAndreas Sandberg <andreas.sandberg@arm.com>
Wed, 5 Jul 2017 14:43:49 +0000 (14:43 +0000)
commit00da08902918da13fccc3f2266b7b2f5d0080708
treeb495a0ceba7e073adca005cf84a7575d0aad5f27
parent0747a432d25ade2c197ca6393270e12606419872
cpu: Added interface for vector reg file

This patch adds some more functionality to the cpu model and the arch to
interface with the vector register file.

This change consists mainly of augmenting ThreadContexts and ExecContexts
with calls to get/set full vectors, underlying microarchitectural elements
or lanes. Those are meant to interface with the vector register file. All
classes that implement this interface also get an appropriate implementation.

This requires implementing the vector register file for the different
models using the VecRegContainer class.

This change set also updates the Result abstraction to contemplate the
possibility of having a vector as result.

The changes also affect how the remote_gdb connection works.

There are some (nasty) side effects, such as the need to define dummy
numPhysVecRegs parameter values for architectures that do not implement
vector extensions.

Nathanael Premillieu's work with an increasing number of fixes and
improvements of mine.

Change-Id: Iee65f4e8b03abfe1e94e6940a51b68d0977fd5bb
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues and CC reg free list initialisation ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2705
65 files changed:
configs/common/cores/arm/O3_ARM_v7a.py
src/arch/SConscript
src/arch/alpha/isa.hh
src/arch/alpha/registers.hh
src/arch/arm/ArmISA.py
src/arch/arm/insts/static_inst.cc
src/arch/arm/insts/static_inst.hh
src/arch/arm/isa.cc
src/arch/arm/isa.hh
src/arch/arm/nativetrace.cc
src/arch/arm/registers.hh
src/arch/arm/remote_gdb.cc
src/arch/arm/remote_gdb.hh
src/arch/arm/utility.cc
src/arch/generic/ISACommon.py [new file with mode: 0644]
src/arch/generic/SConscript
src/arch/generic/traits.hh [new file with mode: 0644]
src/arch/generic/types.hh
src/arch/isa_parser.py
src/arch/mips/isa.hh
src/arch/mips/registers.hh
src/arch/null/registers.hh
src/arch/power/isa.hh
src/arch/power/registers.hh
src/arch/riscv/isa.hh
src/arch/riscv/registers.hh
src/arch/sparc/isa.hh
src/arch/sparc/registers.hh
src/arch/x86/isa.hh
src/arch/x86/registers.hh
src/cpu/base_dyn_inst.hh
src/cpu/checker/cpu.hh
src/cpu/checker/cpu_impl.hh
src/cpu/checker/thread_context.hh
src/cpu/exec_context.hh
src/cpu/inst_res.hh
src/cpu/minor/dyn_inst.cc
src/cpu/minor/exec_context.hh
src/cpu/minor/scoreboard.cc
src/cpu/minor/scoreboard.hh
src/cpu/o3/O3CPU.py
src/cpu/o3/comm.hh
src/cpu/o3/cpu.cc
src/cpu/o3/cpu.hh
src/cpu/o3/dyn_inst.hh
src/cpu/o3/free_list.hh
src/cpu/o3/inst_queue_impl.hh
src/cpu/o3/regfile.cc
src/cpu/o3/regfile.hh
src/cpu/o3/rename.hh
src/cpu/o3/rename_impl.hh
src/cpu/o3/rename_map.cc
src/cpu/o3/rename_map.hh
src/cpu/o3/thread_context.hh
src/cpu/o3/thread_context_impl.hh
src/cpu/reg_class.cc
src/cpu/reg_class.hh
src/cpu/reg_class_impl.hh
src/cpu/simple/base.cc
src/cpu/simple/exec_context.hh
src/cpu/simple_thread.hh
src/cpu/static_inst.hh
src/cpu/thread_context.cc
src/cpu/thread_context.hh
src/sim/serialize.cc