Add support for SystemVerilog unique, unique0, and priority case
authorClifford Wolf <clifford@clifford.at>
Thu, 23 Feb 2017 15:33:19 +0000 (16:33 +0100)
committerClifford Wolf <clifford@clifford.at>
Thu, 23 Feb 2017 15:33:19 +0000 (16:33 +0100)
commit00dba4c197b7e3b6c1d1f7b90ae7b1e6172b1e5f
tree552c7c6bdf17dcae25439f8c1b32df1960da1b35
parent1e927a51d575c19b85db2c73ff70d8a244eb1fb5
Add support for SystemVerilog unique, unique0, and priority case
frontends/verilog/verilog_lexer.l
frontends/verilog/verilog_parser.y