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(parent: fc7da1b) | patch
compat: provide verilog.convert shim.
authorwhitequark <whitequark@whitequark.org>
Fri, 21 Dec 2018 13:53:06 +0000 (13:53 +0000)
committerwhitequark <whitequark@whitequark.org>
Fri, 21 Dec 2018 13:53:06 +0000 (13:53 +0000)
commit00ef7a78d38f542c39488df918e42013bbc65c56
tree883e9c5b6a2d608ab86e16a359b920820c410d0etree
parentfc7da1be2d7e30fb1eea570418d8660249f9987ecommit | diff
compat: provide verilog.convert shim.
nmigen/compat/fhdl/conv_output.py [new file with mode: 0644] blob
nmigen/compat/fhdl/verilog.py [new file with mode: 0644] blob