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(parent: 41c51d7) | patch
add a 2nd clock, this one deliberately the
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 11 Mar 2022 13:47:13 +0000 (13:47 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 11 Mar 2022 13:47:13 +0000 (13:47 +0000)
commit0107a36d930d4c8dab1099969b140673198d29a4
tree6bc3cce89b605672e45e69c32b44a7b495f6cfedtree
parent41c51d7d185189bac92043aaf1bf1cc2125b48d7commit | diff
add a 2nd clock, this one deliberately the
same frequency as the main one, for now
gram/simulation/crg.py diff | blob | history
gram/simulation/simsoc.py diff | blob | history