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(parent: 7e7e537) | patch
whoops. mode-bits need to be put in MSB0 order. sigh
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 17 Sep 2022 20:47:02 +0000 (21:47 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 17 Sep 2022 20:47:02 +0000 (21:47 +0100)
commit01600a57590f173ff216e1ae6d140ae07fb5ebda
tree26c571e98bd80a1a3558bcb9e41dff097d4cc5d1tree
parent7e7e5372963a4f39564c0f9e6a0c64154702535dcommit | diff
whoops. mode-bits need to be put in MSB0 order. sigh
src/openpower/sv/trans/svp64.py diff | blob | history