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(parent: 1a530cf) | patch
fixup: generated-verilog submodule for experimental Rocket support
authorGabriel L. Somlo <gsomlo@gmail.com>
Thu, 23 May 2019 20:27:17 +0000 (16:27 -0400)
committerGabriel L. Somlo <gsomlo@gmail.com>
Thu, 23 May 2019 22:22:37 +0000 (18:22 -0400)
commit019fd940055a8a81211a93e4f62af486d310962e
treeda9b808fd63ba5dc5d09a403659164ea4e4f79detree
parent1a530cf27d59102791b9d208cb101bd7241739fccommit | diff
fixup: generated-verilog submodule for experimental Rocket support

FIXME: This patch uses https://github.com/gsomlo/rocket-litex-verilog,
however in the long term it would perhaps be better if enjoy-digital
hosted the generated-verilog repository.
Once that's in place, I'd be happy to re-spin (and squash) this patch
on top of its parent -- GLS
.gitmodules diff | blob | history
litex/soc/cores/cpu/rocket/verilog [new submodule] blob