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(parent: ca25e0e) | patch

author	Luke Kenneth Casson Leighton <lkcl@lkcl.net>
	Thu, 11 Oct 2018 20:45:26 +0000 (21:45 +0100)
committer	Luke Kenneth Casson Leighton <lkcl@lkcl.net>
	Thu, 11 Oct 2018 20:45:26 +0000 (21:45 +0100)
commit	0314c19d5bae6ad6f4b6cd6b1b9473b58a7634a5
tree	26c9d4aeb2d216a53d81adae18d68da5585241ad	tree
parent	ca25e0e1b818b48a33e96bba668d439abc06ad33	commit \| diff

redirect instructions through a class called sv_proc_t

preparing the groundwork for a total over-ride of macros such as
WRITE_RD, and so on, so that element width can be implemented

id_regs.py		diff \| blob \| history
riscv/insn_template_sv.cc		diff \| blob \| history
riscv/processor.cc		diff \| blob \| history
riscv/processor.h		diff \| blob \| history
riscv/riscv.mk.in		diff \| blob \| history
riscv/sv_insn_redirect.cc	[new file with mode: 0644]	blob
riscv/sv_insn_redirect.h	[new file with mode: 0644]	blob
sv_proc_gen.py	[new file with mode: 0644]	blob

Simple-V augmented version of spike