back.rtlil: don't cache wires for legalized switch tests.

back.rtlil: don't cache wires for legalized switch tests.

This causes miscompilation of code such as:

  r = Array([self.a, self.b])
  m = Module()
  with m.If(r[self.s]):
      m.d.comb += self.o.eq(1)
  return m