projects / yosys.git / commit
| author | Dan Ravensloft <dan.ravensloft@gmail.com> | |
| Mon, 27 Jul 2020 13:21:05 +0000 (14:21 +0100) | ||
| committer | Marcelina Kościelnicka <mwk@0x04.net> | |
| Thu, 20 Aug 2020 16:25:05 +0000 (18:25 +0200) | ||
| commit | 034b9ec7161d67e861b1befcc4c550bff4481387 | |
| tree | ac014657358681ef44ebd669beacfc8820e3ba2f | tree |
| parent | d9dd8bc74803789835533b81c35c927a80f6c28f | commit | diff |
| techlibs/intel/Makefile.inc | diff | blob | history | |
| techlibs/intel/cyclonev/cells_arith.v | [deleted file] | blob | history |
| techlibs/intel/cyclonev/cells_map.v | [deleted file] | blob | history |
| techlibs/intel/cyclonev/cells_sim.v | [deleted file] | blob | history |
| techlibs/intel/synth_intel.cc | diff | blob | history | |
| techlibs/intel_alm/Makefile.inc | diff | blob | history | |
| techlibs/intel_alm/cyclonev/cells_sim.v | [new file with mode: 0644] | blob |
| techlibs/intel_alm/synth_intel_alm.cc | diff | blob | history |