clk2fflogic: Consistently treat async control signals as negative hold.
authorMarcelina Kościelnicka <mwk@0x04.net>
Tue, 7 Jul 2020 12:22:04 +0000 (14:22 +0200)
committerMarcelina Kościelnicka <mwk@0x04.net>
Thu, 9 Jul 2020 16:12:47 +0000 (18:12 +0200)
commit03e28f7ab43116cd4f7fed0e37647637a4d8eda0
treebcbc9cdec25bf44fb89097940743645735a4cfb9
parente9c2c1b7175604acd4285800c441c4bd1d676f9d
clk2fflogic: Consistently treat async control signals as negative hold.

This fixes some dfflegalize equivalence checks, and breaks others — and
I strongly suspect the others are due to bad support for multiple
async inputs in `proc` (in particular, lack of proper support for
dlatchsr and sketchy circuits on dffsr control inputs).
passes/sat/clk2fflogic.cc
tests/techmap/dfflegalize_adff.ys
tests/techmap/dfflegalize_adff_init.ys
tests/techmap/dfflegalize_adlatch.ys
tests/techmap/dfflegalize_adlatch_init.ys
tests/techmap/dfflegalize_dffsr_init.ys
tests/techmap/dfflegalize_sr.ys
tests/techmap/dfflegalize_sr_init.ys