Escape Verilog identifiers for legality outside of Yosys
authorEddie Hung <eddie@fpgeh.com>
Tue, 1 Oct 2019 20:05:56 +0000 (13:05 -0700)
committerEddie Hung <eddie@fpgeh.com>
Tue, 1 Oct 2019 20:05:56 +0000 (13:05 -0700)
commit03ebe43e3edce03d3dc24f80c05e16cdb7b76748
treec429d2f5a067797661be61d65e6b22ec7308afd8
parent1b96d29174d7c56a14031bc117a7da5fa5192c81
Escape Verilog identifiers for legality outside of Yosys
techlibs/xilinx/cells_sim.v