projects / litex.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: c615b50) | patch
litesata/example_designs: fix core generation (RAID introduced some changes on the...
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Thu, 25 Jun 2015 22:20:58 +0000 (00:20 +0200)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Thu, 25 Jun 2015 22:20:58 +0000 (00:20 +0200)
commit04c64eb1d88fb5a5ac8f2356fd7f901f4dd2865e
treec9b764c47b7dce5dc1fdc601392c14d186dfe3eftree
parentc615b50735ab5c7f8d655a8474a71301efae64fccommit | diff
litesata/example_designs: fix core generation (RAID introduced some changes on the PHY)
misoclib/mem/litesata/example_designs/platforms/verilog_backend.py diff | blob | history
misoclib/mem/litesata/example_designs/targets/core.py diff | blob | history
misoclib/mem/litesata/phy/__init__.py diff | blob | history