arch-arm: Fix Compare and Swap Pair instructions
authorGiacomo Travaglini <giacomo.travaglini@arm.com>
Wed, 20 Jan 2021 16:13:01 +0000 (16:13 +0000)
committerGiacomo Travaglini <giacomo.travaglini@arm.com>
Sat, 23 Jan 2021 13:04:02 +0000 (13:04 +0000)
commit04ee39a2e80e80168f57bbd64e3f03bd211068d6
tree02d733b090807790e304538a8bfe166608b55351
parent3e628206b0d0156b83e61392eafdbf082857629f
arch-arm: Fix Compare and Swap Pair instructions

Those instructions were broken after:

https://gem5-review.googlesource.com/c/public/gem5/+/38381/4

Which is effectively replacing the generic StaticInst src and dest
reg array with an instruction specific one.
The size of the array is evaluated by the ISA parser, which is
counting the operands when parsing the isa code.
Alas, Compare and Swap Pair instructions were augmenting the number
of destination and source registers in the C++ world, which is
invisible to the parser. This lead to an out of bounds access
of the arrays.

This patch is fixing this behaviour by defining XResult2, which
is the second compare/result register for a paired CAS

Change-Id: Ie35c26256f42459805e007847896ac58b178fd42
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/39456
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
src/arch/arm/insts/mem64.cc
src/arch/arm/insts/mem64.hh
src/arch/arm/isa/insts/amo64.isa
src/arch/arm/isa/operands.isa
src/arch/arm/isa/templates/mem64.isa