backends/verilog: Add support for memory read port reset and init value.
authorMarcelina Kościelnicka <mwk@0x04.net>
Thu, 27 May 2021 15:50:59 +0000 (17:50 +0200)
committerMarcelina Kościelnicka <mwk@0x04.net>
Thu, 27 May 2021 21:47:42 +0000 (23:47 +0200)
commit055ba748bcf8c77bff15bda0de49c0b4b3722bba
treedb1658fdd2f0dac471b61adb4fec55185935e619
parentaabe1c382e635040d16b6a29c7e2741e8e9d7adf
backends/verilog: Add support for memory read port reset and init value.
backends/verilog/verilog_backend.cc