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(parent: cf20e82) | patch
dev-arm: Add basic support for level sensitive SPIs in GICv2
authorAdrien Pesle <adrien.pesle@arm.com>
Mon, 3 Sep 2018 14:43:24 +0000 (16:43 +0200)
committerGiacomo Travaglini <giacomo.travaglini@arm.com>
Mon, 1 Oct 2018 08:28:51 +0000 (08:28 +0000)
commit058e2cec7c56bf0549efff1df5974799c41cd1be
tree0be3f4915fae6c32e017735bb4bd36cd34c6e2d4tree
parentcf20e8211e2c3f1b2085c949a1e992a1f5d1071ccommit | diff
dev-arm: Add basic support for level sensitive SPIs in GICv2

For level sensitive interrupt IRQ line must be cleared when interrupt is
deasserted. This is not the case for edge-trigerred interrupt.

Change-Id: Ib1660da74a296750c0eb9e20878d4ee64bd23130
Reviewed-on: https://gem5-review.googlesource.com/12944
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
src/dev/arm/gic_v2.cc diff | blob | history
src/dev/arm/gic_v2.hh diff | blob | history