soc/interconnect/wishbone: increase bus error timeout to 1e6 cycles
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Sun, 27 Jan 2019 07:23:44 +0000 (08:23 +0100)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Sun, 27 Jan 2019 07:28:01 +0000 (08:28 +0100)
commit05dcb5cadce88c05e2020a293ea5273396702eb9
tree77dcd73429d2b58d5e9a9fd71b287935e7a7476a
parent02708d3b0f13335e494710f1f62122dcc0a1702d
soc/interconnect/wishbone: increase bus error timeout to 1e6 cycles
litex/soc/interconnect/wishbone.py