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(parent: 5c38668) | patch
DMA: Add IOCache and fix bus bridge to optionally only send requests one
authorAli Saidi <saidi@eecs.umich.edu>
Fri, 10 Aug 2007 20:14:01 +0000 (16:14 -0400)
committerAli Saidi <saidi@eecs.umich.edu>
Fri, 10 Aug 2007 20:14:01 +0000 (16:14 -0400)
commit06a9f58c68b621f082d39299bdb01f59ef68ef0e
tree51d9b7982e124d9acccdd8e8fdd8cecf96c0f83ftree
parent5c38668ed68fae7ed18571571d7855b541c4b039commit | diff
DMA: Add IOCache and fix bus bridge to optionally only send requests one
way so a cache can handle partial block requests for i/o devices.

--HG--
extra : convert_revision : a68b5ae826731bc87ed93eb7ef326a2393053964
16 files changed:
configs/common/Caches.py diff | blob | history
configs/common/FSConfig.py diff | blob | history
configs/example/fs.py diff | blob | history
src/base/range_ops.hh [new file with mode: 0644] blob
src/dev/io_device.hh diff | blob | history
src/mem/Bridge.py diff | blob | history
src/mem/bridge.cc diff | blob | history
src/mem/bridge.hh diff | blob | history
src/mem/bus.cc diff | blob | history
src/mem/bus.hh diff | blob | history
src/mem/cache/BaseCache.py diff | blob | history
src/mem/cache/base_cache.cc diff | blob | history
src/mem/cache/base_cache.hh diff | blob | history
src/mem/cache/cache.hh diff | blob | history
src/mem/cache/cache_builder.cc diff | blob | history
src/mem/cache/cache_impl.hh diff | blob | history