fix/Vivado: don't instantiate wishbone.Converter in add_adapter when not needed
Fixes an issue with Vivado which crashes with SIGSEGV when building litex-buildenv at:
https://github.com/antmicro/litex-buildenv/commit/
cc003bef3ac1407f9788ec8b7cc52d5981f8364a
and litex bumped to
4a18b828bc81522a654f51a73f20faece4dc313c,
with options:
CPU=mor1kx; CPU_VARIANT=linux; PLATFORM=arty; FIRMWARE=linux; TARGET=net
The only difference in Verilog is that we avoid creating new Interface and doing
`new_interface.connect(interface)`, so this shouldn't make any difference, but
this somehow generates the error in Vivado (tested on v2018.3 and v2019.2).