fix/Vivado: don't instantiate wishbone.Converter in add_adapter when not needed
authorJędrzej Boczar <jboczar@antmicro.com>
Mon, 20 Jul 2020 13:17:56 +0000 (15:17 +0200)
committerJędrzej Boczar <jboczar@antmicro.com>
Mon, 20 Jul 2020 13:26:21 +0000 (15:26 +0200)
commit07bc589c414fb036ccdaee87b77aa4725123dfc6
tree14e703381c5ae4b65fb189d7d0929f1f3bbd9a5e
parent4a18b828bc81522a654f51a73f20faece4dc313c
fix/Vivado: don't instantiate wishbone.Converter in add_adapter when not needed

Fixes an issue with Vivado which crashes with SIGSEGV when building litex-buildenv at:
https://github.com/antmicro/litex-buildenv/commit/cc003bef3ac1407f9788ec8b7cc52d5981f8364a
and litex bumped to 4a18b828bc81522a654f51a73f20faece4dc313c,
with options:
    CPU=mor1kx; CPU_VARIANT=linux; PLATFORM=arty; FIRMWARE=linux; TARGET=net
The only difference in Verilog is that we avoid creating new Interface and doing
`new_interface.connect(interface)`, so this shouldn't make any difference, but
this somehow generates the error in Vivado (tested on v2018.3 and v2019.2).
litex/soc/integration/soc.py