MEM: Separate queries for snooping and address ranges
authorAndreas Hansson <andreas.hansson@arm.com>
Tue, 17 Jan 2012 18:55:09 +0000 (12:55 -0600)
committerAndreas Hansson <andreas.hansson@arm.com>
Tue, 17 Jan 2012 18:55:09 +0000 (12:55 -0600)
commit07cf9d914b292008ead7021182ec2ef8fc4671f1
treef99ab26383bcdde2f8761af1e75a431d7a84c634
parent142380a373e28cd61b79d348361ec1ed4ed330e5
MEM: Separate queries for snooping and address ranges

This patch simplifies the address-range determination mechanism and
also unifies the naming across ports and devices. It further splits
the queries for determining if a port is snooping and what address
ranges it responds to (aiming towards a separation of
cache-maintenance ports and pure memory-mapped ports). Default
behaviours are such that most ports do not have to define isSnooping,
and master ports need not implement getAddrRanges.
54 files changed:
src/arch/x86/interrupts.cc
src/arch/x86/interrupts.hh
src/arch/x86/pagetable_walker.cc
src/arch/x86/pagetable_walker.hh
src/cpu/base.cc
src/cpu/base.hh
src/cpu/inorder/resources/cache_unit.cc
src/cpu/inorder/resources/cache_unit.hh
src/cpu/o3/cpu.hh
src/cpu/ozone/front_end.hh
src/cpu/ozone/front_end_impl.hh
src/cpu/ozone/lw_lsq.hh
src/cpu/ozone/lw_lsq_impl.hh
src/cpu/simple/atomic.cc
src/cpu/testers/memtest/memtest.cc
src/cpu/testers/memtest/memtest.hh
src/cpu/testers/networktest/networktest.cc
src/cpu/testers/networktest/networktest.hh
src/dev/arm/gic.cc
src/dev/arm/gic.hh
src/dev/arm/pl111.cc
src/dev/arm/pl111.hh
src/dev/copy_engine.hh
src/dev/io_device.cc
src/dev/io_device.hh
src/dev/pciconfigall.cc
src/dev/pciconfigall.hh
src/dev/pcidev.cc
src/dev/pcidev.hh
src/dev/sinic.cc
src/dev/sparc/iob.cc
src/dev/sparc/iob.hh
src/dev/uart8250.cc
src/dev/uart8250.hh
src/dev/x86/i8042.cc
src/dev/x86/i8042.hh
src/dev/x86/i82094aa.hh
src/dev/x86/intdev.cc
src/dev/x86/intdev.hh
src/kern/tru64/tru64_events.cc
src/mem/bridge.cc
src/mem/bridge.hh
src/mem/bus.cc
src/mem/bus.hh
src/mem/cache/base.cc
src/mem/cache/base.hh
src/mem/cache/cache.hh
src/mem/cache/cache_impl.hh
src/mem/physical.cc
src/mem/physical.hh
src/mem/port.hh
src/mem/ruby/system/RubyPort.cc
src/mem/tport.hh
src/sim/system.hh