fhdl/verilog: fix signedness rules for comparison
authorSebastien Bourdeauducq <sebastien@milkymist.org>
Wed, 26 Jun 2013 20:45:47 +0000 (22:45 +0200)
committerSebastien Bourdeauducq <sebastien@milkymist.org>
Wed, 26 Jun 2013 20:45:47 +0000 (22:45 +0200)
commit080afdc3f9db811d7b53dd0da33d122219c594fd
tree0b46642ef2de80bf88988fb944d2d1fe173ba3d7
parent0224ea01cb83d26885514c1c8b9270399d1cf4c5
fhdl/verilog: fix signedness rules for comparison
migen/fhdl/verilog.py