Fix verilog pre-processor for multi-level relative includes
authorClifford Wolf <clifford@clifford.at>
Tue, 14 Mar 2017 16:27:28 +0000 (17:27 +0100)
committerClifford Wolf <clifford@clifford.at>
Tue, 14 Mar 2017 16:30:20 +0000 (17:30 +0100)
commit088f9c9cab8db27076385e6f3242369499247b9f
treedaeb306f9ac20a26e89c99d12df9a0171dac0056
parentc8553539866128279897336795f00248eb527ffa
Fix verilog pre-processor for multi-level relative includes
frontends/verilog/preproc.cc