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(parent: a98e1ad) | patch
build/microsemi/libero_soc: associate timings constraints with synthesis/place&route...
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Fri, 23 Nov 2018 08:30:13 +0000 (09:30 +0100)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Fri, 23 Nov 2018 08:30:13 +0000 (09:30 +0100)
commit09a1cda943440107ddab7ea10814ffdd5ba3a0cd
tree8421a969befd51fd33e9e73cda895b0649e9e3dctree
parenta98e1ad68979eb1974e01f217c5c97c3a11dbe73commit | diff
build/microsemi/libero_soc: associate timings constraints with synthesis/place&route/timing verification
litex/build/microsemi/libero_soc.py diff | blob | history