PowerPC: Create new MMA instruction masks and use them
authorPeter Bergner <bergner@linux.ibm.com>
Wed, 20 Jul 2022 23:16:05 +0000 (18:16 -0500)
committerPeter Bergner <bergner@linux.ibm.com>
Thu, 21 Jul 2022 19:53:52 +0000 (14:53 -0500)
commit0a246853439422e12a0ccb9191be638aab3987eb
tree4f478ea2b8881dfce23cfd2c918ce8cd1b2d33a2
parent8f29211c3f0a6335c17e0a90396c146facf6dba4
PowerPC: Create new MMA instruction masks and use them

The MMA instructions use XX3_MASK|3<<21 as an instruction mask, but that
misses the RC bit/bit 31, so if we disassemble a .long that represents an
MMA instruction except that it also has bit 31 set, we will erroneously
disassemble it to that MMA instruction.  We create new masks defines that
contain bit 31 so that doesn't happen anymore.

opcodes/
* ppc-opc.c (XACC_MASK, XX3ACC_MASK): New defines.
(P_GER_MASK, xxmfacc, xxmtacc, xxsetaccz, xvi8ger4pp, xvi8ger4,
xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger, xvi4ger8pp, xvi4ger8,
xvi16ger2spp, xvi16ger2s, xvbf16ger2pp, xvbf16ger2, xvf64gerpp,
xvf64ger, xvi16ger2, xvf16ger2np, xvf32gernp, xvi8ger4spp, xvi16ger2pp,
xvbf16ger2np, xvf64gernp, xvf16ger2pn, xvf32gerpn, xvbf16ger2pn,
xvf64gerpn, xvf16ger2nn, xvf32gernn, xvbf16ger2nn, xvf64gernn: Use them.
opcodes/ppc-opc.c