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(parent: bdc6ba0) | patch
Add clean_zerowidth pass, use it for Verilog output.
authorMarcelina Kościelnicka <mwk@0x04.net>
Sat, 11 Dec 2021 15:07:29 +0000 (16:07 +0100)
committerMarcelina Kościelnicka <mwk@0x04.net>
Sun, 12 Dec 2021 18:56:50 +0000 (19:56 +0100)
commit0aad88a2fb23e5481538122e1bd4c0fac9ba5e90
tree707e70353574c9d21e903810e6e8823727e21a15tree
parentbdc6ba019ca12a3f3d4cfb1a4d64652538b7c5efcommit | diff
Add clean_zerowidth pass, use it for Verilog output.

This should remove instances of zero-width sigspecs in the netlist,
avoiding problems in the Verilog backend with emitting them.

See #3103.
backends/verilog/verilog_backend.cc diff | blob | history
passes/cmds/Makefile.inc diff | blob | history
passes/cmds/clean_zerowidth.cc [new file with mode: 0644] blob