hdl.ast: allow sampling ClockSignal, ResetSignal.
authorwhitequark <cz@m-labs.hk>
Thu, 17 Jan 2019 05:23:06 +0000 (05:23 +0000)
committerwhitequark <cz@m-labs.hk>
Thu, 17 Jan 2019 05:23:06 +0000 (05:23 +0000)
commit0b21a74f4e08686f2a472d3575392ce86b69f28e
treedfdfa0c34d50566bffd6f15aa2f24e328e1e78e7
parent9567180df404167776b2d948cd7f7ab36e3fc579
hdl.ast: allow sampling ClockSignal, ResetSignal.
nmigen/hdl/ast.py
nmigen/hdl/xfrm.py
nmigen/test/test_hdl_ast.py