projects / litex.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 6bb22df) | patch
soc/cores/spi: add optional aligned mode.
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Wed, 22 Apr 2020 11:15:07 +0000 (13:15 +0200)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Wed, 22 Apr 2020 11:15:51 +0000 (13:15 +0200)
commit0b3c4b50fa99cd92ba83ea64a1386b94195a35d4
tree48cefea7c7ded602ca34457e174126ea6433f280tree
parent6bb22dfe6b8f4b9550c9b2b169228c9c991fa78fcommit | diff
soc/cores/spi: add optional aligned mode.

In aligned mode, MOSI and MISO bits are located on the LSBs and first transmitted MOSI bit is length - 1 bit.
litex/soc/cores/spi.py diff | blob | history
test/test_spi.py diff | blob | history