sim: pass extra keyword arguments to Verilog converter
authorSebastien Bourdeauducq <sebastien@milkymist.org>
Mon, 30 Apr 2012 21:38:17 +0000 (16:38 -0500)
committerSebastien Bourdeauducq <sebastien@milkymist.org>
Mon, 30 Apr 2012 21:38:17 +0000 (16:38 -0500)
commit0b62e573aea43087e6f98ae762d32939c4766583
treeb8c3841c71e49b4b0ce4fbafc2d1e62ccc19c0ac
parent6a52e44d09afeadc7727f9a0cc9ebe405469360e
sim: pass extra keyword arguments to Verilog converter
doc/index.rst
migen/sim/generic.py