RISC-V: Add Sign/Zero extend patterns for PIC loads

RISC-V: Add Sign/Zero extend patterns for PIC loads

Loads on RISC-V are sign-extending by default, but we weren't telling
GCC this in our PIC load patterns.  This corrects the problem, and adds
a zero-extending pattern as well.

gcc/ChangeLog

2017-10-25  Palmer Dabbelt  <palmer@dabbelt.com>

       * config/riscv/riscv.md (ZERO_EXTEND_LOAD): Define.
       * config/riscv/pic.md (local_pic_load): Rename to local_pic_load_s,
       mark as a sign-extending load.
       (local_pic_load_u): Define.

From-SVN: r254092