cores/clock/S7PLL: fix -1/-3 speedgrade vco max freq swap
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Fri, 9 Aug 2019 07:27:32 +0000 (09:27 +0200)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Fri, 9 Aug 2019 07:27:32 +0000 (09:27 +0200)
commit0c287b11ba11b24eaba6cf19282ac7b074720b3c
treef95d5569c58f4ceab03456174f28ed658f928ecb
parent82cd557c24914db627c93ae2599068cf05429367
cores/clock/S7PLL: fix -1/-3 speedgrade vco max freq swap
litex/soc/cores/clock.py