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(parent: 68ff56e) | patch
compat: provide verilog.convert shim.
authorwhitequark <cz@m-labs.hk>
Fri, 21 Dec 2018 13:53:06 +0000 (13:53 +0000)
committerwhitequark <cz@m-labs.hk>
Fri, 21 Dec 2018 13:53:06 +0000 (13:53 +0000)
commit0c985fead287218c5eee2bab97c4bc621cc7210d
tree883e9c5b6a2d608ab86e16a359b920820c410d0etree
parent68ff56eced33feaf991dfb8c91aad47723bb0b85commit | diff
compat: provide verilog.convert shim.
nmigen/compat/fhdl/conv_output.py [new file with mode: 0644] blob
nmigen/compat/fhdl/verilog.py [new file with mode: 0644] blob