projects / yosys.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: e7bec9b) | patch
Work around DDR dout sim glitches in ice40 SB_IO sim model
authorClifford Wolf <clifford@clifford.at>
Sun, 7 Feb 2016 10:19:48 +0000 (11:19 +0100)
committerClifford Wolf <clifford@clifford.at>
Sun, 7 Feb 2016 10:19:48 +0000 (11:19 +0100)
commit0ccfb88728c5bdf167b1d672034ca5cf360dedb1
tree13f2f434d9d7ae720067df7d400f98b40df64b1btree
parente7bec9bbb8ca9dd58c8a2fbf7ea0d2010fc40f5fcommit | diff
Work around DDR dout sim glitches in ice40 SB_IO sim model
techlibs/ice40/cells_sim.v diff | blob | history