xilinx-mult: Move some registers later in the data flow
authorPaul Mackerras <paulus@ozlabs.org>
Mon, 6 Sep 2021 23:32:30 +0000 (09:32 +1000)
committerPaul Mackerras <paulus@ozlabs.org>
Sat, 11 Sep 2021 03:27:46 +0000 (13:27 +1000)
commit0cdaa2778f95102fef5a16f6a98aef01cab381b8
treec37b02d11c2b540eba6e511ca8d716ab9c922115
parent09bd01a49e15e9de1382c666ef794e48df5d3ea7
xilinx-mult: Move some registers later in the data flow

This changes s0 to use the P register rather than the A/B/C input
registers, thus improving the timing of the multiplier output.  The
m00, m02 and m03 multipliers now use their P registers rather than the
M registers, moving the addition they do from the second cycle to the
first.

Also, the XOR that inverts the 32 LSBs is moved before the output
register.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
xilinx-mult.vhdl