git.libre-soc.org Git - yosys.git/commit

author	whitequark <whitequark@whitequark.org>
	Tue, 14 Apr 2020 12:34:35 +0000 (12:34 +0000)
committer	whitequark <whitequark@whitequark.org>
	Tue, 14 Apr 2020 12:36:20 +0000 (12:36 +0000)
commit	0d0bf9c4a2acd70418670518bf641f7628c92165
tree	8e1b8e2265368f8dedcb3aad577680b6f00078d8	tree
parent	f44b287f8e36684607447beb05556f1a5a34d625	commit \| diff

write_cxxrtl: ignore disconnected module ports.

E.g. port `q` in `submod x(.p(p), .q());`.

Fixes #1920.