Move \init from source wire to submod if output port
authorEddie Hung <eddie@fpgeh.com>
Tue, 26 Nov 2019 00:07:47 +0000 (16:07 -0800)
committerEddie Hung <eddie@fpgeh.com>
Tue, 26 Nov 2019 00:07:47 +0000 (16:07 -0800)
commit0d7ba77426b5ede6eae76059d8182ab096041ff2
treeb342bb2dad10eaa2670e9d043e9545f165f0b4e6
parentdd317c92808a73e61e771a123fc4377d3fb78af2
Move \init from source wire to submod if output port
passes/hierarchy/submod.cc