Sign extend port connections where necessary
authorZachary Snow <zach@zachjs.com>
Fri, 18 Dec 2020 19:59:08 +0000 (12:59 -0700)
committerZachary Snow <zach@zachjs.com>
Sat, 19 Dec 2020 03:33:14 +0000 (20:33 -0700)
commit0d8e5d965f2585e6ed151a9e92d83ee63df6172a
treef2da85bd5aaf90406d3536b64749837d44003eab
parent40e35993af6ecb6207f15cc176455ff8d66bcc69
Sign extend port connections where necessary

- Signed cell outputs are sign extended when bound to larger wires
- Signed connections are sign extended when bound to larger cell inputs
- Sign extension is performed in hierarchy and flatten phases
- genrtlil indirects signed constants through signed wires
- Other phases producing RTLIL may need to be updated to preserve
  signedness information
- Resolves #1418
- Resolves #2265
frontends/ast/genrtlil.cc
passes/hierarchy/hierarchy.cc
passes/techmap/flatten.cc
tests/various/port_sign_extend.v [new file with mode: 0644]
tests/various/port_sign_extend.ys [new file with mode: 0644]