gen/sim/core: do not use reset_less clock_domains for the one that are created (logic...
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Tue, 25 Apr 2017 08:56:19 +0000 (10:56 +0200)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Tue, 25 Apr 2017 08:56:19 +0000 (10:56 +0200)
commit0daeff86896c1951c8737caa25e870eeca8713e2
treeb3bbc76c3c484a2d4659347743817e6761a306f9
parent456cce3ec667c57a94f8add4f75209ec7c669d56
gen/sim/core: do not use reset_less clock_domains for the one that are created (logic may need to access reset signal)
litex/gen/sim/core.py