mem: Modify drain to ensure banks and power are idled
authorWendy Elsasser <wendy.elsasser@arm.com>
Thu, 13 Oct 2016 18:22:11 +0000 (19:22 +0100)
committerWendy Elsasser <wendy.elsasser@arm.com>
Thu, 13 Oct 2016 18:22:11 +0000 (19:22 +0100)
commit0dd0d4ee7adb561e89a47c3e8284c237bebdc4ab
treea82aca322b5ba7be0bb924c7c12424aaeae39f15
parent27665af26d8bfdeaab3f3877da9158c9fc5f93ac
mem: Modify drain to ensure banks and power are idled

Add constraint that all ranks have to be in PWR_IDLE
before signaling drain complete

This will ensure that the banks are all closed and the rank
has exited any low-power states.

On suspend, update the power stats to sync the DRAM power logic

The logic maintains the location of the signalDrainDone
method, which is still triggered from either:
1) Read response event
2) Next request event

This ensures that the drain will complete in the READ bus
state and minimizes the changes required.

Change-Id: If1476e631ea7d5999fe50a0c9379c5967a90e3d1
Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
src/mem/dram_ctrl.cc
src/mem/dram_ctrl.hh