Fixed parsing of module arguments when one type is used for many args
authorClifford Wolf <clifford@clifford.at>
Tue, 19 Nov 2013 19:35:31 +0000 (20:35 +0100)
committerClifford Wolf <clifford@clifford.at>
Tue, 19 Nov 2013 19:35:31 +0000 (20:35 +0100)
commit0dfdbd991afcbcc38110d22d489969ae33fb1f68
treee30b5665c7ed0f0b43c5f7bcdb3b96b960165650
parent63285b300ca8a3057345f6b28ee20ff709ede24d
Fixed parsing of module arguments when one type is used for many args
frontends/verilog/parser.y