Add support for zero-width signals to Verilog back-end, fixes #948
authorClifford Wolf <clifford@clifford.at>
Mon, 22 Apr 2019 17:44:10 +0000 (19:44 +0200)
committerClifford Wolf <clifford@clifford.at>
Mon, 22 Apr 2019 17:44:42 +0000 (19:44 +0200)
commit0e0c80fac883a6f512a94aecdc3c915b8cacb562
tree1b9a402b5151ffb19b85287b4989489ce5c7a77d
parent9050b5e1915b05f55c1db279566f34202905f02a
Add support for zero-width signals to Verilog back-end, fixes #948

Signed-off-by: Clifford Wolf <clifford@clifford.at>
backends/verilog/verilog_backend.cc