gen/sim, fhdl: remove port.we_granularity limitation on simulations
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Wed, 23 Mar 2016 08:46:54 +0000 (09:46 +0100)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Wed, 23 Mar 2016 08:46:54 +0000 (09:46 +0100)
commit0ef1d44c4481bc559c4edcb147b829974d8eb6f3
tree819b03c1a89399be460a3044b0495e97dcf11905
parent9517b9b87052005f5b7133ff741541e58528d030
gen/sim, fhdl: remove port.we_granularity limitation on simulations

We have to find a way to eliminate all replaced memory ports from specials,
here we use a workaround and remove remaining _MemPorts before simulating.

If possible, proper way would be to remove replaced ports from specials.
Another solution can to remove all ports that are no longer associated with
a Memory.
litex/gen/fhdl/simplify.py
litex/gen/sim/core.py