x86: decode instructions with vex prefix
authorNilay Vaish <nilay@cs.wisc.edu>
Fri, 17 Jul 2015 16:31:22 +0000 (11:31 -0500)
committerNilay Vaish <nilay@cs.wisc.edu>
Fri, 17 Jul 2015 16:31:22 +0000 (11:31 -0500)
commit0ef3dcc27b0fd03df0aa38a4af05bf536be29c49
tree9a3494b6304b6139524340c2ce6e9d5e869a7028
parentfc5bf6713f191047e07f33a788d099b2bbd9faf4
x86: decode instructions with vex prefix

This patch updates the x86 decoder so that it can decode instructions with vex
prefix. It also updates the isa with opcodes from vex opcode maps 1, 2 and 3.
Note that none of the instructions have been implemented yet. The
implementations would be provided in due course of time.
src/arch/x86/decoder.cc
src/arch/x86/decoder.hh
src/arch/x86/decoder_tables.cc
src/arch/x86/isa/bitfields.isa
src/arch/x86/isa/decoder/decoder.isa
src/arch/x86/isa/decoder/vex_opcodes.isa [new file with mode: 0644]
src/arch/x86/isa_traits.hh
src/arch/x86/types.cc
src/arch/x86/types.hh