projects / litex.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 5a16a5b) | patch
update clock constraints for SATA1 and use sys_clk of 200MHz
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Wed, 17 Dec 2014 17:03:11 +0000 (18:03 +0100)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Wed, 17 Dec 2014 18:24:23 +0000 (19:24 +0100)
commit0f8f89a269240659a06ed04eff68d9adf8ebf406
tree19b640874e499a49c9032ad5404957cbd49958d5tree
parent5a16a5b46daa15a4b6ef01488e274c8fc21df2c5commit | diff
update clock constraints for SATA1 and use sys_clk of 200MHz
- data seems stable (mila capture) except when receive the ALIGN primtive from the device, we should maybe disable alignment on the HOST when link is ready...
lib/sata/phy/k7sataphy/crg.py diff | blob | history
platforms/kc705.py diff | blob | history
targets/test.py diff | blob | history
test/test_stim.py diff | blob | history