mem: Make cache terminology easier to understand
authorAndreas Hansson <andreas.hansson@arm.com>
Thu, 31 Dec 2015 14:32:58 +0000 (09:32 -0500)
committerAndreas Hansson <andreas.hansson@arm.com>
Thu, 31 Dec 2015 14:32:58 +0000 (09:32 -0500)
commit0fcb376e5fc6bc0a7b16dc4595d4a7e3f910cbc8
tree4be665e3596d9d4e193e6354c5577ee0077732da
parenta3177645773b8eb4b835050c395554d3e2b4664a
mem: Make cache terminology easier to understand

This patch changes the name of a bunch of packet flags and MSHR member
functions and variables to make the coherency protocol easier to
understand. In addition the patch adds and updates lots of
descriptions, explicitly spelling out assumptions.

The following name changes are made:

* the packet memInhibit flag is renamed to cacheResponding

* the packet sharedAsserted flag is renamed to hasSharers

* the packet NeedsExclusive attribute is renamed to NeedsWritable

* the packet isSupplyExclusive is renamed responderHadWritable

* the MSHR pendingDirty is renamed to pendingModified

The cache states, Modified, Owned, Exclusive, Shared are also called
out in the cache and MSHR code to make it easier to understand.
28 files changed:
src/cpu/o3/cpu.cc
src/dev/dma_device.cc
src/mem/abstract_mem.cc
src/mem/addr_mapper.cc
src/mem/bridge.cc
src/mem/cache/base.hh
src/mem/cache/blk.hh
src/mem/cache/cache.cc
src/mem/cache/cache.hh
src/mem/cache/mshr.cc
src/mem/cache/mshr.hh
src/mem/cache/mshr_queue.cc
src/mem/cache/mshr_queue.hh
src/mem/coherent_xbar.cc
src/mem/comm_monitor.cc
src/mem/dram_ctrl.cc
src/mem/dramsim2.cc
src/mem/hmc_controller.cc
src/mem/mem_checker_monitor.cc
src/mem/noncoherent_xbar.cc
src/mem/packet.cc
src/mem/packet.hh
src/mem/ruby/system/DMASequencer.cc
src/mem/ruby/system/RubyPort.cc
src/mem/serial_link.cc
src/mem/simple_mem.cc
src/mem/snoop_filter.cc
src/mem/tport.cc