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(parent: 1ec5994) | patch
verilog: fix sizing of ports with int types in module headers
authorZachary Snow <zach@zachjs.com>
Mon, 1 Mar 2021 18:31:25 +0000 (13:31 -0500)
committerZachary Snow <zach@zachjs.com>
Mon, 1 Mar 2021 18:39:05 +0000 (13:39 -0500)
commit10a6bc9b81d1c2236e80a608778c904aebe54c28
treebc9d0dd7f4893a2a132a7672e5a7f57db1a72726tree
parent1ec5994100510d6fb9e18ff7234ede496f831a51commit | diff
verilog: fix sizing of ports with int types in module headers

Declaring the ports as standard module items already worked as expected.
This adds a missing usage of `checkRange()` so that headers such as
`module m(output integer x);` now work correctly.
frontends/verilog/verilog_parser.y diff | blob | history
tests/verilog/port_int_types.sv [new file with mode: 0644] blob
tests/verilog/port_int_types.ys [new file with mode: 0644] blob