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(parent: c69db91) | patch
Add Verilog source location information to `AST_POSEDGE` and `AST_NEGEDGE` nodes.
authorAlberto Gonzalez <boqwxp@airmail.cc>
Fri, 17 Apr 2020 06:16:59 +0000 (06:16 +0000)
committerAlberto Gonzalez <boqwxp@airmail.cc>
Fri, 17 Apr 2020 06:16:59 +0000 (06:16 +0000)
commit10a814f97808de8cce7e50a03f01832db66c263e
tree44afa7d32f1137ebfe1a2f7048fdc4c28579ba8ftree
parentc69db910acef73bbd5a1bfb015231fce5419e0afcommit | diff
Add Verilog source location information to `AST_POSEDGE` and `AST_NEGEDGE` nodes.
frontends/verilog/verilog_parser.y diff | blob | history