sim: riscv: invert sim_state storage
authorMike Frysinger <vapier@gentoo.org>
Thu, 13 May 2021 09:44:02 +0000 (05:44 -0400)
committerMike Frysinger <vapier@gentoo.org>
Mon, 17 May 2021 05:02:09 +0000 (01:02 -0400)
commit10c23a2c6fec069ef8279fc19f625348da70cd0d
treecf41d7afc62bb9f64c08aa8fb9fb9a57456c8bde
parent2ad10cb22246b16fdebece06646db288dbea1fdb
sim: riscv: invert sim_state storage
sim/riscv/ChangeLog
sim/riscv/interp.c
sim/riscv/sim-main.c
sim/riscv/sim-main.h