projects / yosys.git / commit
| author | Clifford Wolf <clifford@clifford.at> | |
| Thu, 14 Mar 2013 10:15:00 +0000 (11:15 +0100) | ||
| committer | Clifford Wolf <clifford@clifford.at> | |
| Thu, 14 Mar 2013 10:15:00 +0000 (11:15 +0100) | ||
| commit | 11789db206276edf50f45f8d82e094a87643630c | |
| tree | 273617ebcc76baca97a426345aeb0ae835073f6a | tree |
| parent | de823ce964b93c0746b81867b29228cdbe00aae6 | commit | diff |
| backends/verilog/verilog_backend.cc | diff | blob | history | |
| techlibs/simlib.v | diff | blob | history |