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(parent: 4b4cd03) | patch
X86: Add L1 caches for the TLB walkers.
authorGabe Black <gblack@eecs.umich.edu>
Wed, 2 Feb 2011 02:28:41 +0000 (18:28 -0800)
committerGabe Black <gblack@eecs.umich.edu>
Wed, 2 Feb 2011 02:28:41 +0000 (18:28 -0800)
commit119f5f8e94e673b1495dccce03b54773dc18afea
treeff11fb58d39d12bd7c4fa5d94f629d718fe4e2ectree
parent4b4cd0303ea0e3b23e641933dbf0da57d1483764commit | diff
X86: Add L1 caches for the TLB walkers.

Small L1 caches are connected to the TLB walkers when caches are used. This
allows them to participate in the coherence protocol properly.
configs/common/CacheConfig.py diff | blob | history
configs/common/Caches.py diff | blob | history
src/cpu/BaseCPU.py diff | blob | history
src/cpu/o3/O3CPU.py diff | blob | history