Add $lut support to Verilog back-end
authorClifford Wolf <clifford@clifford.at>
Wed, 5 Sep 2018 22:18:01 +0000 (00:18 +0200)
committerClifford Wolf <clifford@clifford.at>
Wed, 5 Sep 2018 22:18:01 +0000 (00:18 +0200)
commit12440fcc8f705c117b5f91fae24b7e5c4fbf8560
treea9955d3cd62399c8c4d5b612dd4717cc6729c2c1
parent5d9d22f66d512d33b2c1a13c4f1a20f944e6acc3
Add $lut support to Verilog back-end

Signed-off-by: Clifford Wolf <clifford@clifford.at>
backends/verilog/verilog_backend.cc